Recently, research and development have been actively conducted on a display device using an electro-optical element such as organic EL or EP. Particularly, the organic EL display is the focus of attention in view of possible applications in mobile phones, PDAs Personal Digital Assistants), and like mobile devices, to exploit its low voltage/low power consumption.
FIG. 14 illustrates a pixel circuit disclosed in Patent document 1, as the structure of an organic EL display drive circuit.
A pixel circuit 300 illustrated FIG. 14 includes four p-type TFTs (Thin Film Transistors) 360, 365, 370, 375, two capacitors 350, 355, and an OLED (organic EL) 380. The TFTs 365 and 375 and the organic EL (OLED) 380 are connected in series between a power supply line 390 and a common cathode (GND). The capacitor 350 and the switching TFT 360 are connected in series between a gate terminal of the driver TFT 365 and a data line 310. The switching TFT 370 is present between the gate terminal and a drain terminal of the driver TFT 365. The capacitor 355 is present between the gate terminal and a source terminal of the driver TFT 365. The gate terminals of the TFTs 360, 370, 375 are connected respectively to a select line 320, an auto-zero line 330, and a lighting line 340.
In this pixel circuit 300, the auto-zero line 330 and the lighting line 340 go GL (LOW) during the first period. This turns on the switching TFTs 370, 375, placing the drain terminal and gate terminal of the driver TFT 365 at the same potential. The driver TFT 365 is therefore turned on, allowing a current flow from the driver TFT 365 to the OLED 380.
At this moment, the data line 310 is fed with reference voltage, and the select line 320 is set to GL which in turn keeps at reference voltage one of terminals of the capacitor 350 that connects to the TFT 360.
During the second period, the lighting line 340 is set to GH(HIGH), turning off the TFT 375.
The gate voltage of the driver TFT 365 then gradually increases. As the gate voltage reaches a value (VDD+Vth) corresponding to the threshold voltage Vth of the driver TFT 365 (Vth<0), the driver TFT 365 is turned off.
During the third period, the auto-zero line 330 is set to GH, turning off the switching TFT 370. Thus, the capacitor 350 holds the difference between its gate voltage and the reference voltage.
In other words, the gate voltage of the driver TFT 365 is equal to a value VDD+Vth corresponding to the threshold voltage Vth when the reference voltage is on the data line 310. If the voltage on the data line 310 changes from the reference voltage, a current in accordance with the change needs to flow through the driver TFT 365, regardless of the threshold voltage of the driver TFT 365.
To this end, the voltage on the data line 310 is changed by that desired amount. The select line is set to HIGH, turning off the switching TFT 360. The capacitor 355 maintains the gate voltage of the driver TFT 365. This ends a select period for the pixel.
Thus, the use of the pixel circuit illustrated in FIG. 14 allows for compensation for variations of the threshold voltage Vth of the driver TFT 365, and supply of the voltage (desired potential-threshold potential) obtained by the compensation to the gate terminal of the driver TFT 365.
However, the pixel circuit illustrated in FIG. 14 causes voltage drop at the switching TFT 375, which increases power consumption. This is because the driver TFT 365, the switching TFT 375, the organic EL OLED are connected in series between the power supply line 390 and the common cathode (GND).
For the reduction of the voltage drop, it is effective to increase a gate width of the switching TFT 375.
This increases a gate size of the switching TFT 375 and decreases an aperture ratio in a bottom emission structure (structure in which light is taken from the TFT substrate side).
Further, higher definition is difficult to achieve in a top emission structure (structure in which light is taken from the side opposite to the TFT substrate side).
Especially, this problem becomes more pronounced in fabricating TFTs with low-mobility amorphous Si.
In view of this, Non-patent document 1 discloses the arrangement in which a driver TFT and an organic EL are directly coupled between a power supply line and a common electrode, but no switching TFT is disposed therebetween. A pixel circuit illustrated in FIG. 15 is the pixel circuit disclosed in Non-patent document 1.
The pixel circuit illustrated in FIG. 15 is composed of four n-type TFTs T1 through T4, a capacitor Cs, and an organic EL OLED. The organic EL OLED and the driver TFT T4 are directly connected in series between a common electrode GND and a power supply line COM. The switching TFT T3 is disposed between a gate terminal a and a drain terminal c of the driver TFT T4. The capacitor Cs and the switching TFT T1 are disposed in series between the gate terminal of the driver TFT T4 and a data line DAT. The switching TFT T2 is disposed between the power supply line COM and a node b of the capacitor Cs and the switching TFT T1.
Control lines SCT, MRG, RST are connected to the switching TFTs T1 through T3, respectively.
FIG. 16 illustrates operations of the power supply line COM and the control lines MRG, RST, SCT.
In the pixel circuit in FIG. 15, the power supply line COM is first fed with a voltage Vp. Since a voltage of the gate terminal a of the driver TFT T4 is higher than that of a terminal c of the driver TFT T4, the driver TFT T4 is turned on and a current is flown from the power supply line COM to the organic EL OLED. As a result of this, the voltage of the terminal c takes a positive value and a reverse voltage is applied to the organic EL OLED.
Then, the control line RST is set to GH, turning on the switching TFT T3. With this, the voltage of the gate terminal a of the driver TFT T4 becomes equal to the voltage of the terminal c (i.e. voltage of the power supply line COM>voltage of the terminal c), which turns off the driver TFT T4. At this moment, voltage Vg (with reference to anode voltage GND of the OLED) of the gate terminal a is required to be higher than threshold voltage Vth of the driver TFT T4.
Next, a voltage of the power supply line COM is set to 0V. At this moment, voltages of the gate terminal a and the terminal c are higher than the threshold voltage Vth of the driver TFT T4. This flows a current from the gate terminal a to the power supply line COM, and a difference in voltage between the gate terminal a and the power supply line COM becomes voltage Vth. A difference in voltage between the one end of the capacitor Cs and the other thereof becomes Vth.
Next, the control line MRG is set to GL to turn off the switching TFT T2, while the control line SCT is set to GH to turn on the switching TFT T1. Then, the terminal b is fed with required voltage Vda from the data line DAT.
At this moment, since a reverse voltage is applied to the organic EL OLED, the organic EL OLED serves as a capacitor. This causes the terminal a to be varied in voltage according to the variation of the voltage of the terminal b.
That is, when Co is capacitance of the organic EL OLED and Cs is capacitance of the capacitor Cs,
            (              Vth        -        0            )        +          (              Vth        -        0            )        =                                          (                          Vx              -              Vda                        )                    ⁢          Cs                +                              (                          Vx              -              0                        )                    ⁢          Co                    ⁢                          ∴                        Vth          ⁡                      (                          Cs              +              Co                        )                          +                  Vda          ·          Cs                      =                            Vx          ⁡                      (                          Cs              +              Co                        )                          ⁢                                  ∴        Vx            =              Vth        +                  Vda          ·                      Cs            /                          (                              Cs                +                Co                            )                                          
Further, difference between the voltage of the gate terminal a of the driver TFT T4 and the voltage of the terminal b is expressed by the following equation:
      Vx    -    Vda    =            Vth      +              Vda        ·                  Cs          /                      (                          Cs              +              Co                        )                              -      Vda        =          Vth      -              Vda        ·                  Co          /                      (                          Cs              +              Co                        )                              
Then, the control line SCT is set to GL to turn off the switching TFT T1, so that the voltage of the gate terminal a is held.
Thereafter, the control line RST is set to GL to turn off the switching TFT T3, and the control line MRG is set to GH to turn off the switching TFT T2.
Further, a voltage of the power supply line COM is set to −VDD.
As a result of this, gate-to-source voltage Vgs of the driver TFT T4 (voltage between the terminal a and the power supply line COM) is kept Vx−Vda.
That is, when Vda<0, the driver TFT T4 is turned on. When Vda≧0 the driver TFT T4 is turned off.
Whether the driver TFT T4 is turned on or off, the voltage of the drain terminal c is higher than the voltage of the source terminal (power supply line COM). When Vda<0, and drain-to-source voltage Vds of the driver TFT T4 is higher than gate-to-source voltage Vgs of the driver TFT T4, a current corresponding to Vgs is flown from the drain terminal of the driver TFT T4 to the source terminal thereof. Then, the current is supplied from the GND through the organic EL OLED.
Thus, the use of the pixel circuit illustrated in FIG. 15 in which the organic EL OLED and the driver TFT T4 are directly connected between the common electrode GND and the power supply line COM enables compensation for variation in threshold voltage of the driver TFT T4 and supply of a desired current to the organic EL OLED.
FIG. 17 illustrates the structure of the pixel circuit disclosed in Patent document 2.
As illustrated in FIG. 17, in this pixel circuit, a driver TFT 106 and an organic EL 107 are directly connected between a GND line and a power supply line 109. A switching TFT 108 is disposed between a gate and a drain of the driver TFT 106 (Herein, GND line side of the driver TFT 106 is a drain terminal). Switching TFTs 111 and 104 are disposed in series in this order between the gate terminal of the driver TFT 106 and the data line 103. A capacitor 105 is disposed between the source terminal of the driver TFT 106 and a node of the switching TFT 111 and the switching TFT 104. A scanning line 112 is connected to the respective gate terminals of the switching TFTs 108 and 111, and a scanning line 110 is connected to a gate terminal of the switching TFT 104.
Note that the TFTs 104, 106, 111 are n-type TFTs, and the TFT 108 is a p-type TFT.
The operation of the pixel circuit illustrated in FIG. 17 can be described with reference to FIGS. 18(a) through 18(d).
That is, as illustrated in FIG. 18(a), to begin with, the scanning line 110 is set to a negative voltage to turn off the switching TFT 104, while the scanning line 112 is set to a positive voltage to turn off the switching TFT 108 and turn on the switching TFT 111. Then, a negative voltage of a power supply line 109 is changed to a positive voltage. At this moment, the organic EL 107 operates as a capacitor (because the organic EL 107 is fed with a reverse voltage). According to difference in voltage between the organic EL 107 and the capacitor 105, a gate terminal of the driver TFT 106 becomes a positive voltage, and the driver TFT 106 is turned on. This allows electric charge to flow from the anode terminal of the organic EL 107 to the GND line. Then, the voltage of the source terminal of the driver TFT 106 approaches GND voltage, and the driver TFT 106 is turned off.
Next, as illustrated in FIG. 18(b), the scanning line 112 is set to negative voltage to turn off the switching TFT 111 and turn on the switching TFT 108. This allows the gate terminal of the driver TFT 106 to have GND voltage.
Subsequently, by changing positive voltage of the power supply line 109 to GND voltage, the source terminal of the driver TFT 106 becomes highly negative voltage. This allows a gate-to-source voltage of the driver TFT 106 to be positive voltage, which turns on the driver TFT 106. Then, electric charge is supplied from the drain terminal to the source terminal of the driver TFT 106, which turns a gate-to-source voltage of the driver TFT 106 to threshold voltage −Vth. This turns off the driver TFT 106.
By the way, at the time when the switching TFT 111 is turned off, a voltage of the scanning line 110 is set to positive voltage to turn on the switching TFT 104. As illustrated in FIG. 18(c), voltage Vd1 corresponding to luminance of the organic EL 107 is fed from the data line 103 to a terminal (other terminal) of the capacitor 105 on the switching TFT 104 side.
As a result of this, GND voltage is fed to the gate terminal of the driver TFT 106, a voltage of the source terminal of the driver TFT 106 becomes −Vth, and voltage Vd1 is fed to the other terminal of the capacitor 105.
Then, as illustrated in FIG. 18(d), after the scanning line 110 is set to negative voltage to turn off the switching TFT 104, the scanning line 112 is set to positive voltage to turn off the switching TFT 108 and turn on the switching TFT 111.
As a result of this, a gate-to-source voltage of the driver TFT 106 turns Vd1+Vth. Thus, it is possible to control the driver TFT 106 to flow a current corresponding to voltage Vd1 regardless of the threshold voltage Vth of the driver TFT 106.
[Patent document 1]
Japanese PCT National Phase Unexamined Patent Publication No. 514320/2002 (published on May 14, 2002)
[Patent document 2]
Japanese PCT National Phase Unexamined Patent Publication No. 280059/2004 (published on Oct. 7, 2004)
[Non-patent document 1]
IDW '03, pp. 255-258 (held on Dec. 3 to 5, 2003).